Field of the Invention
The present invention relates to a shift register and, more particularly, to a shift register capable of reducing size of a display apparatus through reduction in the falling edge time of a scan pulse.
Discussion of the Related Art
In general, a liquid crystal display (LCD) device is adapted to display an image by adjusting light transmittance of a liquid crystal using an electric field. To this end, the LCD device includes a liquid crystal panel having pixel areas arranged in matrix form, and a driving circuit for driving the liquid crystal panel.
In the liquid crystal panel, a plurality of gate lines and a plurality of data lines are arranged to cross each other, and the pixel areas are defined respectively at intersections of the gate lines and the data lines. Also pixel electrodes and a common electrode for applying the electric field to the respective pixel areas are formed in the liquid crystal panel.
Each of the pixel electrodes is connected to an associated one of the data lines via the source electrode and drain electrode of a thin film transistor (TFT), which is a switching device. The TFT is turned on in response to a scan pulse applied to the gate electrode thereof via an associated one of the gate lines, so as to charge a data signal on the associated data line to the pixel electrode.
The driving circuit includes a gate driver for driving the gate lines, a data driver for driving the data lines, a timing controller for supplying control signals for control of the gate driver and data driver, and a power supply for supplying various drive voltages to be used in the LCD device.
The gate driver sequentially supplies scan pulses to the gate lines to sequentially drive liquid crystal cells in the liquid crystal panel on a line-by-line basis. In order to sequentially output the above-mentioned scan pulses, the gate driver includes a shift register.
In a conventional case, the shift register includes a plurality of stages each having a plurality of switching elements.
Each stage includes a buffer as an output unit thereof. The output unit includes output switching elements (buffer transistors) for outputting scan pulses, that is, a pull-up switching element and a pull-down switching element. When such an output switching element is degraded due to prolonged driving thereof, the wavelength of a scan pulse generated from the output switching element may become distorted. For example, the falling edge time of the scan pulse may be increased.
This will be described in detail with reference to FIG. 1.
FIG. 1 is a diagram explaining problems caused by an increase in falling edge time of a scan pulse in a conventional case.
FIG. 1 depicts waveforms of a source output enable signal (SOE) to determine output timing of a data signal Vdata and a scan pulse Vgate output from a shift register. The scan pulse Vgate is supplied to a gate line and controls operation of a pixel switching element connected to the gate line.
When the falling edge time of a scan pulse applied to a gate line connected to a specific pixel is lengthened, the turn-on time of a pixel switching element in the specific pixel is lengthened and a data signal other than a data signal associated with the particular pixel (a data signal associated with a pixel other than the specific pixel) may be input to the specific pixel. As a result, the pixel may display an erroneous image and degradation of picture quality may occur.
The above-mentioned problem may be overcome through an increase in size of output switching elements. However, by increasing the size of the output switching elements, the size of the shift register is also increased. As such, there may be another problem in that the size of the display apparatus equipped with the shift register is increased.